MOSFET fabricated on Silicon-On-Insulator (SOI) substrate has significant advantages such as higher speed, lower power and higher density than on bulk silicon wafer substrate. SOI substrate consists of a thin surface layer of single crystal silicon on an underlayer of insulating material on a bulk silicon wafer. The thin surface silicon layer, typically a few tens of nanometers to several microns thick, is the silicon channel of the transistor. The insulating layer, usually made of silicon dioxide, is referred to as the buried oxide and is usually a few hundreds of nanometers thick.
SOI wafers improve the transistor performance by reducing the operating silicon volume and by isolating the transistors. The thin surface silicon layer limits the volume of silicon that needs to be charged to switch the transistor on and off, and therefore reduces the parasitic capacitance of the transistor and increases the switching speed. The insulating layer isolates the transistor from its neighbors, and therefore reduces the leakage current and allows the transistor to operate at lower supply voltages and thus the transistors can be smaller and more densely packed.
For CMOS technology in the sub-50 nm, the silicon channel and the buried oxide thickness need to be much less than 50 nm and 100 nm, respectively, in order to prevent short channel effect. A super SOI with silicon film thickness of 5 nm and buried oxide thickness of 20 nm may be capable of suppressing short channel effect at the CMOS down scaling limit of 20 nm channel length. However, these requirements on the thickness of the silicon and buried oxide films exceed the present manufacturing capabilities of SOI wafers. Furthermore, the device performance can be improved with an insulator having lower dielectric constant, which cannot be achieved with a buried oxide. The lowest dielectric constant for the insulator layer is 1, meaning an air gap under the silicon layer, and the improved device is called silicon-on-nothing (SON) device. SON device simulation on theoretically proposed device shows improved performance over SOI device with buried oxide having a dielectric constant of 3.9 (see R. Koh, “Buried layer engineering to reduce the drain-induced barrier lowering of sub-0.05 μm SOI-MOSFET”, Japanese Journal of Applied Physics, Vol. 38 (1999), pp. 2294–2299, Part 1, No. 4B, April 1999).
Various SON device fabrication processes have been proposed with the source and drain areas connected to the substrate. Though these devices show improved performances, their device structures could lead to higher parasitic source and drain capacitance, together with a potential concern of subsurface punch through. For examples, see                M. Jurczak, T. Skotnicki, M. Paoli, B. Tormen, J. Martins, J. L. Regolini, D. Dutartre, P. Ribot, D. Lenoble, R. Pantel, S. Monfray, “Silicon-on-nothing (SON)—an innovative process for advanced CMOS”, IEEE Transactions on Electron Devices, Vol. 47, No. 11, November 2000, pp. 2179–2187;        S. Monfray, T. Skotnicki, Y. Morand, S. Descombes, M. Paoli, P. Ribot, A. Talbot, D. Dutartre, F. Leverd, Y. Lefriec, R. Pantel, M. Haond, D. Renaud, M-E. Nier, C. Vizioz, D. Louis, N. Buffet, “First 80 nm SON (silicon-on-nothing) MOSFETs with perfect morphology and high electrical performance”, IEDM Tech. Dig., 2001, p. 800; and        T. Sato, H. Nii, M. Hatano, K. Takenaka, H. Hayashi, K. Ishigo, T. Hirano, K. Ida, N. Aoki, T. Ohguro, K. Ino, I. Mizushima, Y. Tsunashima, “SON (silicon-on-nothing) MOSET using ESS (empty space in silicon) technique for SoC application”, IEDM Tech. Dig., 2001, p. 809.        
Shown in FIG. 1A is the prior art SON device comprising a gate electrode 8, a gate dielectric 7, source 4, and drain 5 through the device channel 6, together with the source and drain extensions 4a and 5a on a silicon substrate 1. The SON device is isolated by trench isolation 3 and floated on an air gap 2. However, the air gap 2 is limited to the device channel 6 and the source and drain extensions 4a and 5a. The source 4 and drain 5 are still connected to the silicon substrate 1. FIG. 1B shows the top view of the prior art SON device.